Logic synthesis

Results: 291



#Item
11Electronic engineering / Digital electronics / Electronic design automation / Hardware description languages / Electronics / Logic synthesis / Verilog / High-level synthesis / VHDL / SystemC / Adder / Silicon compiler

Functional Design using Behavioural and Structural Components Richard Sharp University of Cambridge Computer Laboratory William Gates Building JJ Thomson Avenue

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Source URL: rich.recoil.org

Language: English - Date: 2006-04-13 14:58:00
12Theoretical computer science / Formal methods / Logic in computer science / Electronic design automation / NP-complete problems / Boolean algebra / Boolean satisfiability problem / Solver / Formal equivalence checking / Formal verification / Model checking / Uclid

Continued Relevance of Bit-Level Verification Research R. Brayton, N. Een, A. Mishchenko Berkeley Verification and Synthesis Research Center EECS Dept., University of California, Berkeley Introduction

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Source URL: fm.csl.sri.com

Language: English - Date: 2010-10-30 02:14:08
13Constraint programming / Constraint / Constraint logic programming / Constraint satisfaction

A Calculus for Conjecture Synthesis Moa Johansson1 , Lucas Dixon2 , and Alan Bundy3 1 Dipartimento di Informatica, Universit` a degli Studi di Verona ??

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Source URL: www.cse.chalmers.se

Language: English - Date: 2015-08-18 04:15:46
14Formal methods / Theoretical computer science / Logic in computer science / Systems engineering / Formal verification / Specification / Formal specification / Verification / Simulink / Device driver synthesis and verification

Formal Technical Process Specification and Verification for Automated Production Systems Georg Hackenberg, Alarico Campetelli, Christoph Legat, Jakob Mund, Sabine Teufl and Birgit Vogel-Heuser

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Source URL: sdl-forum.org

Language: English - Date: 2014-10-14 21:17:20
15Software testing / Formal methods / Logic in computer science / Theoretical computer science / Program analysis / Software verification / Formal verification / Static program analysis / Model checking / Requirement / Device driver synthesis and verification / Runtime verification

Microsoft Word - f1488_1.doc

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Source URL: ti.arc.nasa.gov

Language: English
16Formal methods / Logic in computer science / Model checking / Theoretical computer science / Formal verification / Safety / Liveness / Device driver synthesis and verification

SimGrid MC 101 Getting Started with the SimGrid Model-Checker Da SimGrid Team September 1, 2015

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Source URL: simgrid.gforge.inria.fr

Language: English - Date: 2015-09-29 06:27:30
17Mathematical optimization / Constraint programming / Logical consequence / Statements / Theorem / Constraint / Constraint logic programming / Constraint satisfaction

Journal of Automated Reasoning manuscript No. (will be inserted by the editor) Conjecture Synthesis for Inductive Theories Moa Johansson · Lucas Dixon · Alan Bundy

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Source URL: www.cse.chalmers.se

Language: English - Date: 2012-03-21 07:54:00
18Electronic design automation / Electronic design / Integrated circuits / Electronic engineering / Logic design / High-level synthesis / Integrated circuit design / Logic simulation / Field-programmable gate array / System on a chip / Application-specific integrated circuit

Microsoft PowerPoint - HLSLessons2.ppt

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Source URL: mesl.ucsd.edu

Language: English - Date: 2009-06-15 02:15:38
19Subroutines / Hardware description languages / Electronic design automation / Electronic engineering / High-level synthesis / Hardware verification languages / Verilog / VHDL / Logic synthesis / Inline expansion / Parameter / Recursion

Hardware Synthesis using SAFL and Application to Processor Design (Invited Talk) Alan Mycroft1,2 and Richard Sharp1 1

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Source URL: rich.recoil.org

Language: English - Date: 2006-04-13 14:58:00
20Electronic engineering / Electronics / Electronic design automation / Electronic design / System on a chip / Fabless semiconductor companies / Hardware description languages / Logic synthesis / Synopsys / FPGA prototyping / Field-programmable gate array / High-level synthesis

Datasheet Synplify Pro and Premier Fast, Reliable FPGA Implementation and Debug Overview

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Source URL: www.synopsys.com

Language: English - Date: 2016-02-10 05:16:04
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